The present invention relates to electronic circuits, and more particularly, to phase frequency detectors that generate signals having minimum pulse widths.
A phase-locked loop (PLL) is an electronic circuit with a voltage or current driven oscillator that is constantly adjusted to match in phase (and thus lock on) the frequency of a reference clock signal. In addition to stabilizing a particular communications channel by keeping it set to a particular frequency, a PLL can be used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency.
A PLL typically includes a phase frequency detector (PFD), a charge pump, and a loop filter in addition to the oscillator. The PFD generates pulses in it output signals in response to the difference between the phase and frequency of a reference clock signal and a feedback clock signal from the oscillator. When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals. When the PFD does not generate pulses in lock mode, the charge pump does not provide charge to the loop filter. As a result, charge leaks away from the loop filter, and the control voltage on the loop filter drifts away from a stable value.
To prevent the control voltage from drifting, most PLLs provide a well defined minimum short pulse width in the output signals of the PFD. However, a PFD that generates a minimum pulse width in lock mode is more sensitive to small differences in the phases of the reference clock signal and the feedback clock signal.
If the minimum pulse of the PFD is too narrow, the PLL has a larger static phase error. If the minimum pulse of the PFD is too wide, the PLL has a longer lock time. If the up and down charge pump current sources are not equal, a wider minimum pulse from the PFD can amplify any difference in the charge that is provided to and removed from loop filter when the PLL is in lock mode. As a result, a minimum pulse that is too wide can introduce more offset into the PLL loop.
Therefore, it would be desirable to provide a phase frequency detector that has a controllable minimum pulse width.